In semiconductor manufacturing, ion implantation is used to change the material properties of portions of a substrate. Indeed, ion implantation has become a standard technique for altering properties of semiconductor wafers during the production of various semiconductor-based products. Implantation may be used to introduce conductivity-altering impurities, modifying crystal surfaces (pre-amorphization), to created buried layers (halo implants) to create gettering sites for contaminants, to create diffusion barriers (F and C implant. Also, implantation may be used in semiconductors for non-transistor applications such as for alloying metal contact area, in flat panel display manufacturing and surface treatment. All of these ion implantation applications may be classified generally as forming a region of material property modification.
In an ion implantation process, a desired impurity material is ionized in an ion source, the resulting ions are accelerated to form an ion beam of a prescribed energy, and the ion beam is directed at a surface of a target substrate, such as a semiconductor-based wafer. Energetic ions in the ion beam penetrate into bulk semiconductor material of the wafer and are embedded into a crystalline lattice of the semiconductor material to form a region of desired conductivity.
Ion implantation systems usually include an ion source for converting a gas or a solid material into a well-defined ion beam. The ion beam may be mass analyzed to eliminate undesired species, is accelerated to a desired energy, and is directed to a target area, typically a wafer of semiconductor material. The ion beam may be distributed over the target area by beam scanning, by target area movement, or by a combination of beam scanning and target area movement. The target may be set to a prescribed angle and orientation relative to the ion beam. Examples of prior art ion implanters are disclosed in U.S. Pat. No. 4,276,477 issued Jun. 30, 1981 to Enge; U.S. Pat. No. 4,283,631 issued Aug. 11, 1981 to Turner; U.S. Pat. No. 4,899,059 issued Feb. 6, 1990 to Freytsis et al.; U.S. Pat. No. 4,922,106 issued May 1, 1990 to Berrian et al.; and U.S. Pat. No. 5,350,926 issued Sep. 27, 1994 to White et al.
A semiconductor manufacturer's profitability may be directly affected by its ability to maintain high yields. A manufacturer's yield refers to a percentage of silicon wafer area that may be successfully processed into usable microelectronic devices (processors, memory cells, or other transistor-based, semiconductor components). Due to a high cost of silicon wafers and a high expense of processing equipment, it is desirable for manufacturers to maintain high yield rates. As an example, if a single wafer may support 300 devices, and each device has a wholesale value of $150, the value of a single processed wafer may be up to $45,000 if the entire usable surface area could be processed into usable devices—i.e., a yield of 100%. Typically, yields must remain above 70% in order for a manufacturer to achieve profitability or even viability, and even slight improvements in yields may translate into significant increases in profitability. In the semiconductor device manufacturing industry, due to a relatively low incremental cost of making more good, i.e., usable, products on each wafer, a primary goal is to maximize yields.
One factor that greatly affects yield is a manufacturer's process control. Therefore, it is critical to ensure that manufacturing equipment is operating consistently and at correct operating parameters. Eliminating process variations generally improves and ideally maximizes yields.
In the case of ion implantation equipment, there are typically four device parameters that a semiconductor manufacturer typically adjusts for its application: ion beam angle, ion dose, ion species, and ion energy. there are in addition to these adjustable parameters, implant equipment setting that can be adjusted, all of which impact semiconductor device performance and which may vary from implant tool to implant tool. Current techniques involve calibrating individual settings of individual implanters, making measurements of system settings, or using non-device blanket wafers. Using these techniques which focus on calibrating implanters one at a time, it is impossible to calibrate accurately. Moreover, calibrating implanters one at a time is time consuming, requires costly wafers, and is difficult to correlate to device yields.
In view of the foregoing, it would be desirable to provide a technique for reducing tool-to-tool performance variation which overcomes some or all of the above-described inadequacies and shortcomings of known systems.